1. Field of the Invention
The present invention is generally in the field of semiconductors. More particularly, the invention is in the field of bipolar and CMOS device fabrication.
2. Background Art
As Bipolar Complementary-Metal-Oxide-Semiconductor (BiCMOS) technology continues to advance in an effort to achieve increased device speed and reduced power consumption, it becomes more difficult to integrate high performance bipolar devices, such as high performance NPN transistors, with CMOS devices, such as P-channel FETs (PFETs) and N-channel FETs (NFETs). High performance NPN devices, such as NPN silicon-germanium (SiGe) bipolar transistors, require a high thermal budget for epitaxial SiGe base formation, while CMOS devices require a low thermal budget to preserve dopant profiles after implanted regions, such as lightly doped drain (LDD) regions, have been formed.
In a conventional BiCMOS process flow, gate electrodes are formed in a CMOS region of a substrate, which includes N wells, P wells, and isolation regions. After formation of the gate electrodes, LDD regions are implanted in the substrate adjacent to the gate electrodes. At this point in the conventional BiCMOS process flow, the CMOS devices are substantially completed and bipolar device formation begins in a bipolar region of the substrate. During bipolar device formation, the collector, epitaxial base layer, and polycrystalline silicon emitter are sequentially formed.
However, the formation of the epitaxial base layer, such as a SiGe epitaxial base layer, requires a high thermal budget, which adversely affects the CMOS devices. For example, the high thermal budget required to form the SiGe epitaxial base layer can adversely affect the junction profiles of the previously formed LDD regions adjacent to the gate electrodes in the CMOS region of the substrate. Furthermore, as bipolar and CMOS devices are scaled down in size in advanced BiCMOS processes, CMOS device formation requires an even lower thermal budget to sustain ultra-shallow junction profiles.
Thus, there is a need in the art for a BiCMOS process flow that allows a sufficiently high thermal budget for bipolar device formation without adversely affecting CMOS device formation.